Strain Decoupling in Ge/Si via Selective Misfit-Network Etching

CMOS-compatible Ge/Si heterostructures enable high-performance electroabsorption modulators, photodetectors, photonic interconnects, and multijunction photovoltaics, yet their scalability is hindered by the 4.2% lattice and thermal mismatch that generates dense dislocations. Here, we report a selective electrochemical process that forms a sub-nanometric (~15 Å) two-dimensional free surface (2DFS) at the Ge/Si interface by etching along the misfit dislocation network. This interfacial gap elastically decouples the Ge epilayer, achieving full strain relaxation, eliminating observable threading dislocations, and enhancing room-temperature photoluminescence while maintaining a smooth, device-compatible surface. Finite-element simulations, porosity–rate calibration, and HAADF-STEM analysis collectively establish the etching conditions and process window for wafer-scale realization of defect-free Ge/Si integration.