A 4–5 GHz Sub-Sampling PLL with TDC-Free Digital Coarse Loop

This paper proposes a sub-sampling phase-locked loop (SSPLL) that combines a time-to-digital converter (TDC)-free digital coarse loop with a high-gain analog SSPD fine loop. The coarse loop follows a counter-assisted, frequency-domain DPLL framework with an auxiliary FLL, enabling wide capture range and fast initial acquisition. Precise fractional-N operation without a TDC is achieved by reusing the fine loop delta–sigma modulator (DSM) and digital-to-time converter (DTC) in the coarse loop: the DSM maps the frequency control word (FCW) fraction to a variable integer sequence for integer-domain fractional synthesis, while the DTC aligns reference clock to the nearest oscillator edge to cancel DSM-induced quantization error. An LMS-based DTC gain calibration is enabled in the coarse loop, and its calibrated gain is handed off to the fine loop, stabilizing loop switching despite the narrow locking range of the SSPD. Constraining arithmetic to the integer path eliminates a need of TDC and simplifies hardware, improving area efficiency while preserving accurate frequency/phase alignment. Simulations in 28 nm CMOS over 4–5 GHz with a 104 MHz reference demonstrate 177-fs RMS jitter, −245.6 dB FoM, 0.146-mm2 active area, and 8.94 mW power, validating wide capture, low in-band phase noise, and robust coarse-to-fine handover.