Statistical Modeling of Timing Variability Due to Random Telegraph Noise in Logic Gates

In MOS transistors of nanometer dimensions, stochastic performance variations arise not only from factors related to the fabrication process, which do not change over the lifetime of the device. These include variability of physical dimensions, doping profiles and material granularity (e.g., metal grain granularity). Besides these time-zero variability effects, other factors that lead to performance variation from one instant in time to the other start playing a significant role. Random Telegraph Noise is among these relevant time-dependent variability sources. Due to the intrinsic nature of Random Telegraph Noise, each device has a different stochastic behavior of the threshold voltage over time. In this work, we model the statistical parameters of the electrical performance variations induced by Random Telegraph Noise. The area scaling of this performance variability is detailed and discussed, supporting designers in transistor sizing toward a more reliable design. Additionally, it is demonstrated that it is possible to exploit sensitivity analysis with the analytical model presented, to implement automated, fast and accurate estimations of the time-dependent performance variability of devices, logic gates and circuits composed of MOSFETs. Monte Carlo simulations are run to corroborate the model and illustrate its applicability.