6‐Bit High Precision Compact Inline Switching Attenuator for DC to 15 GHz

ABSTRACT This paper presents a high‐precision, compact 6‐bit digital attenuator with optimal cascade order that utilizes capacitive compensation. An improved topology is proposed, and the common centroid mathematical model of the resistor array is analyzed based on post‐layout simulation, thus further enhancing the performance of the attenuator. The employment of these optimization techniques, in conjunction with the consideration of linearity and impedance variation, has enabled the determination of an optimal cascading sequence for achieving optimal performance. The fabrication of the 6‐bit attenuator utilizes a 65‐nm CMOS process, resulting in a core area of merely 0.0065 mm². It features ultra‐wideband operation with a 31.5 dB tuning range and 0.5 dB adjustment steps. Within the DC‐15 GHz frequency range, the insertion loss of the reference state is found to be between 3.6 and 6.4 dB, and the return loss of all 64 states is below −10 dB. The root mean square (RMS) values of amplitude error and phase error are less than 0.5 dB and 3°.