A standardized approach to characterize hysteresis in 2D-materials-based transistors for stability benchmarking and performance projection

The hysteresis observed in the transfer characteristics of emerging transistors based on 2D-materials is widely accepted as an important metric related to the device quality. However, the specifics of hysteresis characterization measurements are rarely given, and its mechanistic understanding remains fragmentary. Here, we provide a comprehensive theoretical analysis of the dominant mechanisms contributing to hysteresis: charge trapping by defects from the channel or the gate, the drift of mobile charges, and eventually ferroelectricity. We suggest methods to experimentally distinguish between these phenomena and propose a standardized hysteresis measurement scheme to establish the hysteresis as a comparable metric for the assessment of device stability. Our standardized scheme ensures that hysteresis data can be effectively compared across different technologies and, most importantly, provides a means to extrapolate data obtained on thicker prototypes to subnanometer equivalent oxide thicknesses. This facilitates the systematic benchmarking of insulator/channel combinations in terms of stability, which thereby enables the screening of material systems for more stable and reliable 2D-material-based metal-oxide-semiconductor field-effect transistors (MOSFETs).

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Publication Details

Journal
Nature Communications
Published
2025-11-21
DOI
https://doi.org/10.1038/s41467-025-66210-z
Citations
2
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
1.46

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article

A standardized approach to characterize hysteresis in 2D-materials-based transistors for stability benchmarking and performance projection

Yu. Yu. Illarionov, Saptarshi Das, Thomas Mueller, Dmitry K. Polyushkin et al.
2 citations
Nature Communications
Ferroelectric and Negative Capacitance Devices
1.46
article

A standardized approach to characterize hysteresis in 2D-materials-based transistors for stability benchmarking and performance projection

Yu. Yu. Illarionov, Saptarshi Das, Thomas Mueller, Dmitry K. Polyushkin, Junchuan Tang, Xiao Renshaw Wang, Seyed Mehdi Sattari‐Esfahlan, Congwei Tan, Pedram Khakbaz, Changze Liu, Y. Li, Theresia Knobloch, Hailin Peng, Joël Kurzweil, Tibor Grasser, Aftab Nazir, Michael Waltl, Alexander Karl, Bernhard Stampfer, Dominic Waldhoer, Yichi Zhang, Mina Bahrami, Yu Zheng, Axel Verdianu, Lorenzo Pettorosso
article en
2 citations

Abstract

The hysteresis observed in the transfer characteristics of emerging transistors based on 2D-materials is widely accepted as an important metric related to the device quality. However, the specifics of hysteresis characterization measurements are rarely given, and its mechanistic understanding remains fragmentary. Here, we provide a comprehensive theoretical analysis of the dominant mechanisms contributing to hysteresis: charge trapping by defects from the channel or the gate, the drift of mobile charges, and eventually ferroelectricity. We suggest methods to experimentally distinguish between these phenomena and propose a standardized hysteresis measurement scheme to establish the hysteresis as a comparable metric for the assessment of device stability. Our standardized scheme ensures that hysteresis data can be effectively compared across different technologies and, most importantly, provides a means to extrapolate data obtained on thicker prototypes to subnanometer equivalent oxide thicknesses. This facilitates the systematic benchmarking of insulator/channel combinations in terms of stability, which thereby enables the screening of material systems for more stable and reliable 2D-material-based metal-oxide-semiconductor field-effect transistors (MOSFETs).

Nature CommunicationsVol. 17(1)
Pennsylvania State University (US), TU Wien (AT), Nanyang Technological University (SG), Peking University (CN), Southern University of Science and Technology (CN), Huawei Technologies (United States) (US)
Ministry of Education, India, Technische Universität Wien, Bộ Giáo dục và Ðào tạo
Openalex Percentile: Top 14%
Ferroelectric and Negative Capacitance Devices
1.46
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