D-latch with optimal cost function in QCA technology

• Quantum-dot cellular automata (QCA) is one of the new technologies in digital circuits and uses nano-sized cells. QCA technology has very high processing power, by placing these quantum cells next to each other, circuits can be designed that are smaller than CMOS circuits and consume less power, and have faster processing. In this article, for the first time, new methods for the design of optimal D-latch, D flip-flop, and shift register circuits are presented, which have the lowest possible number of cells, low time delay, and very low energy consumption. The simple D-latch proposed in this article has only 13 cells, an area of ​​ 0.009 µm 2 and a delay of 0.5 clock cycle, which can be said to be among the most optimal and smallest D-latch. Also, the proposed D-latch with set and reset has 15 cells, an area of 0.01 µm 2 and a delay of 0.5 clock cycle, which has the lowest area and number of cells compared to other designs. For other introduced circuits, we were able to do the best design with the least cell and area. All the simulations of this article have been done with QCADesigner version 2.0.3 software, and the energy consumption of the proposed circuits was measured with QCAPro software. Accurate simulation results show the high validity of the proposed designs. Quantum-dot cellular automata (QCA) is one of the new technologies in digital circuits and uses nano-sized cells. QCA technology has very high processing power, by placing these quantum cells next to each other, circuits can be designed that are smaller than CMOS circuits and consume less power, and have faster processing. In this article, for the first time, new methods for the design of optimal D-latch, D flip-flop, and shift register circuits are presented, which have the lowest possible number of cells, low time delay, and very low energy consumption. The simple D-latch proposed in this article has only 13 cells, an area of ​​ 0.009 µm 2 and a delay of 0.5 clock cycle, which can be said to be among the most optimal and smallest D-latch. Also, the proposed D-latch with set and reset has 15 cells, an area of 0.01 µm 2 and a delay of 0.5 clock cycle, which has the lowest area and number of cells compared to other designs. For other introduced circuits, we were able to do the best design with the least cell and area. All the simulations of this article have been done with QCADesigner version 2.0.3 software, and the energy consumption of the proposed circuits was measured with QCAPro software. Accurate simulation results show the high validity of the proposed designs. Furthermore, the cost function, defined as the product of the area and the square of the delay, shows significant improvements, with an improvement of approximately 70% for the D latch and about 50% for the D flip-flop compared to state-of-the-art designs, indicating the overall efficiency of the proposed architectures.