Numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D: Influence of layer thickness and temperature on device performance

This study presents a comprehensive numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D. The impact of the absorber (CdTe) and buffer (CdS) layer thicknesses, as well as the operating temperature, on key photovoltaic parameters namely open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), and power conversion efficiency (PCE) is systematically analyzed. The results indicate that optimal performance is achieved with a CdTe thickness of 2.5–3.0 μm and a CdS buffer of 10–20 nm. Additionally, device performance slightly degrades at elevated temperatures due to enhanced recombination and carrier mobility reduction. This simulation framework provides predictive guidance for improving real-world CdS/CdTe devices and aligns closely with recent experimental findings.

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Publication Details

Journal
Hybrid Advances
Published
2025-11-21
DOI
https://doi.org/10.1016/j.hybadv.2025.100582
Citations
1
Primary Topic
Chalcogenide Semiconductor Thin Films
Type
article
Field-Weighted Citation Impact
0.73
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article

Numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D: Influence of layer thickness and temperature on device performance

Said Dlimi, Fahd Elmourabit, Yassine Essakali
1 citations
Hybrid Advances
Chalcogenide Semiconductor Thin Films
0.73
article

Numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D: Influence of layer thickness and temperature on device performance

Said Dlimi, Fahd Elmourabit, Yassine Essakali
article en
1 citations

Abstract

This study presents a comprehensive numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D. The impact of the absorber (CdTe) and buffer (CdS) layer thicknesses, as well as the operating temperature, on key photovoltaic parameters namely open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), and power conversion efficiency (PCE) is systematically analyzed. The results indicate that optimal performance is achieved with a CdTe thickness of 2.5–3.0 μm and a CdS buffer of 10–20 nm. Additionally, device performance slightly degrades at elevated temperatures due to enhanced recombination and carrier mobility reduction. This simulation framework provides predictive guidance for improving real-world CdS/CdTe devices and aligns closely with recent experimental findings.

Hybrid AdvancesVol. 12
Chouaib Doukkali University (MA)
Openalex Percentile: Top 21%
Chalcogenide Semiconductor Thin Films
0.73
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Numerical investigation of CdS/CdTe thin-film solar cells using SCAPS-1D: Influence of layer thickness and temperature on device performance — Said Dlimi, Fahd Elmourabit, et al. · Hybrid Advances (2025) | TGRS Research Map | TGRS