Augmented Co-Simulation for Fast Functional and System-Level Verification of HLS Accelerators

Functional verification of accelerator designs generated through High-Level Synthesis (HLS) requires users to write low-level testbenches and feed them to a Register-Transfer Level (RTL) simulator alongside the generated accelerator. Such a manual and error-prone process hinders early design space exploration due to the inherently slow RTL simulation phase, and it is unable to capture the interaction between the host application and the accelerated kernels. We propose two key improvements to the co-simulation process integrated within an HLS tool: a fast and accurate functional simulation methodology that calculates clock cycles during software execution of an annotated HLS intermediate representation, and a system-level co-simulation that couples RTL simulation with software execution of a host application through direct programming interfaces and inter-process communication. Both components augment the HLS verification process, enabling developers to extract kernels to be accelerated from a large application, quickly verify their expected performance after synthesis, and automatically validate their correctness by simulating a full host-accelerator system. Our augmented functional verification methodology is, on average, 7.0x faster than a state-of-the-art method and 36.2x faster than RTL simulation in terms of simulated cycles per second, with high accuracy and minimal memory overhead.