An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications

This article presents the design and implementation of a fully differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) in 65 nm UMC technology, specifically targeting biomedical applications where area efficiency is a critical requirement. The design prioritizes achieving clean and precise first-order Noise Shaping (NS) by integrating a switched-capacitor-based integrator with our proposed C-2C ladder DAC topology, which is instrumental in significantly reducing area consumption. Noise performance is optimized by carefully correlating the capacitances of the integrator and DAC, ensuring precision and stability. To achieve robust operation, the design incorporates a process, voltage, and temperature (PVT)-resilient methodology for all system blocks, providing consistent performance and reliability under challenging conditions and variations in fabrication. The implemented prototype achieves an area efficiency of 0.058 mm 2 , 10.37 ENOB over a 20 kHz Bandwidth, and operates at a 1 MHz sampling rate with a power consumption of 448 μ W . • This research exhibits for the first time, the NS SAR incorporating a C2C DAC. • The design specifications target biomedical applications, with good trade-offs. • The proposed design improves Integration for the NS-SAR. • The design aims for resilience to Process, Voltage, and Temperature Variations. • The experimental results in the Integrated Circuit prototype show the benefits.