A 16-GHz 6.56-mW Slew-Rate-Tolerant Integrating-Mode Phase Interpolator in 12-nm FinFET

This study presents a high-speed, 9-bit integrating-mode phase interpolator (IMPI) in a 12 nm FinFET process. The proposed slew-rate-tolerant design accepts bandwidth-limited inputs, relaxing the stringent need for high-slew-rate clocks found in prior research. This is primarily achieved through an optimized switch design that converts the sinusoidal voltage input into a quasi-square-wave current. A detailed theoretical model identifies asymmetrical clock feedthrough as the dominant nonlinearity, which is suppressed by a cancellation circuit. Furthermore, an adaptive biasing loop is employed to compensate for Process, Voltage, and Temperature (PVT)-induced P/N mismatch. This work is validated through comprehensive post-layout simulations; operating from a 0.8 V supply at 16 GHz, the PI achieves a peak-to-peak Integral Nonlinearity (INL) of 4.3 LSB (530 fs) while consuming 6.56 mW.