Enhanced DC and RF performance of an SOI-MESFET with dual intrinsic layers and a doped channel bottom

In this paper, a proposed structure of SOI-MESFET with two intrinsic semiconductor layers at the top of the channel and an area with additional impurities in the channel bottom (IA-SOI) is presented. In addition to this structure, the transistor, which has only two intrinsic semiconductor layers at the top of the channel (I-SOI), is tested to determine the importance of the layer with more impurities in the channel bottom of IA-SOI. Some of the most important electrical parameters of the proposed transistors are studied and compared with those of the conventional structure (C-SOI). These parameters include drain current, electric field, breakdown voltage, gate-source capacitor, output resistance, maximum output power density and threshold voltage. The two intrinsic semiconductor layers of IA-SOI improve the breakdown voltage of this transistor by 45 % and reduce the gate-source capacitor by 18 % compared to those of the C-SOI. Also, the layer with additional impurities in the channel bottom of the proposed structure increases the drain current by 100 %. Simultaneous increase of drain current and breakdown voltage in IA-SOI significantly increases the maximum power density of this transistor compared to the conventional one. Comparing I-SOI with the conventional structure, it can be concluded that I-SOI increases the output resistance by 100 % compared to that in the C-SOI structure.