Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes

Belief propagation (BP) combined with ordered statistics decoding (OSD) provides a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly universal. However, the complexity of OSD can limit real-time decoding, particularly for superconducting qubits, and the limits of classical hardware decoders have not been fully explored. Therefore, it is important to assess the architecture of OSD for different code families, such as surface codes and bicycle bivariate codes, under realistic assumptions like the detector error model. This paper introduces a BP + OSD parallel architecture implemented on FPGA and ASIC for surface codes (distances 3–21) and bicycle bivariate codes (distances 6–24). Results show that for surface codes up to distance 9, the OSD post-processor fits into a single VCU129 FPGA, achieving a frequency of 200 MHz with a worst-case latency of 134 μs. For bicycle bivariate codes, the limit is distance 12, with a frequency of 244 MHz and a worst-case latency of 84 μs. In ASIC, with 45 nm technology, latency improves by 31%, but area resources grow significantly, making parallel implementation beyond distance 12 impractical on a single chip. The designs were verified using a hardware emulator, ensuring that the decoder’s behavior matches software simulations and revealing interesting results like potential error floors at low logical error rates.