Icy-hot: decoupled compute paradigm towards a general-purpose superconducting CPU design

Introduction Single Flux Quantum (SFQ) superconducting technology offers major performance and energy advantages over CMOS as Dennard scaling wanes. Yet, SFQ CPUs face key challenges: the Josephson Junction (JJ) budget limits manufacturability, and the lack of dense on-chip memory restricts scalability. Control and memory structures dominate JJ usage, motivating new architectures that exploit SFQ strengths while mitigating its limitations. Methods We introduce Icy-Hot, a hybrid CPU architecture that splits computation across two cryogenic zones. The 4 K Icy Zone, implemented with SFQ logic, performs high-speed execution, while the 77 K Hot Zone, built with CMOS, handles fetch, decode, and control. Compiler-inserted metadata and compact SFQ memory structures—a Hot-Driven Register File and a shift-register-based Dependency Buffer—enable decoupled pipeline execution and reduced cross-zone communication. Results Cycle-accurate simulations and SFQ circuit synthesis demonstrate that Icy-Hot achieves a 38% total power improvement over a 77 K CMOS baseline while using only ≈220,000 JJs, an 8× reduction from naïve SFQ cores. Loop-intensive workloads with high operand reuse achieve up to 4.5× performance speedup due to efficient local execution in the Icy Zone. Discussion By co-optimizing cryogenic CMOS and SFQ circuits, Icy-Hot demonstrates a practical path toward scalable, energy-efficient superconducting processors. The design captures SFQ’s intrinsic efficiency while addressing memory and control bottlenecks, marking a foundational step toward general-purpose SFQ CPU architectures.