SPICE-Based Automatic Parasitic Extraction in Double Pulse Test Circuits for SiC MOSFETs

This paper presents an automated method for extracting parasitic elements of SiC MOSFET double pulse test (DPT) circuits. The approach uses the open-source PYLTspice package to simulate the DPT under varying parasitic elements. A differential evolution (DE) optimizer adjusts these parasitic values so that the simulated switching energies ($E_{\text {on }}$ and $E_{\text {off }}$) match the device data sheet’s specified loss curves. The tuned model achieves up to a $92.7 \%$ reduction in error between simulated and data sheet switching loss values, compared to the untuned baseline.This workflow avoids the need for commercial 3D field solvers (e.g., Ansys Q3D or Altium Designer) since the circuit layout is not available and relies entirely on free SPICE tools. The results emphasize that stray, connection, and component placement parasitic inductances have a non-negligible impact on switching performance. Even slight variations in these inductances can cause switching losses to deviate significantly from data sheet values. Incorporating these parasitic elements yields simulated waveforms that closely follow the data sheet curves especially for high current devices, highlighting the importance of modeling parasitic elements in switching device simulations. and in SPICE-based converter and inverter designs to ensure result accuracy.