Constant-Time Modulo: A Secure Hardware Design Against Timing Attacks

In the evolving landscape of cybersecurity and cryptographic hardware, it is critical to ensure resistance against timing side channel attacks. This paper investigates the timing side channel vulnerability in a hardware-friendly modulo algorithm. Through detailed experimental analysis, we demonstrate that the execution time of the existing implementation varies significantly with input values, making it susceptible to timing-based attacks. To address this, we propose a constant-time modulo algorithm that eliminates timing leakage. We further integrate this secure implementation into Number Theoretic Transform (NTT) and Inverse NTT (INTT) modules, key components in signal processing and post-quantum cryptography, and evaluate their performance. Our results show that while the secure design introduces minor area and power overheads, it effectively mitigates timing side channel risks, making it suitable for secure cryptographic hardware applications.