Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing

In-memory computing (IMC) with Resistive Random Access Memory (ReRAM) crossbars has emerged as a promising solution to overcome the von Neumann bottleneck by enabling computation inside memory arrays. This paper presents a unified benchmarking of multi-bit arithmetic circuits in the MAGIC logic style, encompassing seven adder and three multiplier architectures with operand sizes from 8 to 64 bits. Through a proposed parallel mapping methodology, we achieve latency reductions of up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$26.3 \times$</tex> for adders and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$361 \times$</tex> for multipliers relative to state-of-the-art designs, realized through efficient crossbar-level utilization with modest hardware overhead. Our evaluation shows that Brent-Kung (BK) adders are most latencyefficient for larger sizes, while Serial Prefix (SE) adders excel for smaller ones and also offer superior hardware efficiency. In addition, Dadda multipliers achieve the lowest total latency, whereas array multipliers provide the best hardware efficiency among multipliers. By systematically quantifying the trade-offs between latency and memristor count, this work offers a detailed design-space exploration of arithmetic units for ReRAM-based IMC, yielding practical insights for future high-performance, memory-centric architectures.