Design and Prototyping of Custom SHA-3 Instruction for CVA6 RISC-V Core

This paper presents the design, implementation, validation, and performance benchmarking of a custom SHA-3 instruction (shatr) integrated directly into the CPU datapath of a Linux-capable RISC-V System-on-Chip (SoC). While previous research has focused on software simulations or external coprocessors, our work details the full-stack integration into the CVA6 CPU core, implemented and validated entirely on an FPGA hardware prototype. The system is proven to be robust and compatible, successfully booting a standard Linux operating system and passing the complete suite of NIST SHA-3 cryptographic validation tests. Experimental results demonstrate that the shatr instruction provides an average performance gain of 155.21x for short inputs, 157.20x for long inputs over standard ISA execution of SHA-3 workloads. This acceleration is achieved with a minimal area overhead of 3.3% in LUTs and 1.5% in registers, with no degradation to the system’s maximum clock frequency and with no added critical path latency. This work provides a concrete, hardware-proven reference for SHA-3-based cryptographic extensions in open-source RISC-V platforms, bridging the gap between microarchitectural theory and practical, system-level deployment for SHA-3 acceleration.