Matrix-Vectorized Canonical Signed Digit Quantized Neural Networks for Efficient Forward Pass Simulation

Quantized neural networks (QNNs) reduce computational cost but typically rely on multiplications, which limits their efficiency. Canonical Signed Digit (CSD) representation eliminates the need for multipliers through signed shifts. We present a matrix-vectorized Python framework for efficient batch forward-pass evaluation of CSD-QNNs, achieving near-lossless accuracy (absolute errors 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup>, MSE 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup>) and robustness across 8 - 16 bit quantization, while highlighting hardware potential for shift-and-add implementations in FPGA/ASIC deployments.

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Publication Details

Published
2025-10-28
DOI
https://doi.org/10.1109/norcas66540.2025.11231307
Primary Topic
Numerical Methods and Algorithms
Type
article
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article

Matrix-Vectorized Canonical Signed Digit Quantized Neural Networks for Efficient Forward Pass Simulation

Jari Nurmi, M. Ijaz Khan
Numerical Methods and Algorithms
article

Matrix-Vectorized Canonical Signed Digit Quantized Neural Networks for Efficient Forward Pass Simulation

Jari Nurmi, M. Ijaz Khan
article en

Abstract

Quantized neural networks (QNNs) reduce computational cost but typically rely on multiplications, which limits their efficiency. Canonical Signed Digit (CSD) representation eliminates the need for multipliers through signed shifts. We present a matrix-vectorized Python framework for efficient batch forward-pass evaluation of CSD-QNNs, achieving near-lossless accuracy (absolute errors 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup>, MSE 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup>) and robustness across 8 - 16 bit quantization, while highlighting hardware potential for shift-and-add implementations in FPGA/ASIC deployments.

Tampere University (FI)
Openalex Percentile: Top 64%
Numerical Methods and Algorithms
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