Automatic Verification of Analog and Mixed-Signal Neural Network Accelerators and Matrix Multipliers

Analog matrix multiplication circuits containing multiple 10's of thousands of synapse and neuron circuits build the backbone of analog and mixed-signal neural network accelerators. The sheer number of circuit instances in combination with the stochastic nature of neural networks leads to a long simulation and verification runtime whilst functional verification and performance simulations are needed during sign-off to ensure a correct design. Optimized simulations and performance computations are therefore needed. In this work, we present a step-by-step approach to automatically simulate, evaluate and verify such circuits based on specification driven test pattern generation, characterization of neural network building blocks and reduction in netlist size by separation of memory and processing elements. The proposed approach reduces the runtime for full verification and performance evaluation from years using conventional SPICE simulations to days, at similar verification accuracy.