Automatic Reference Clock Duty Cycle Calibration System for Dual Edge Sampling RF Circuits

Duty cycle error of the sampling clock may cause distortion or gain and phase error in RF dual edge samplers, downconverting analog-to-digital converters and time-interleaved sampler arrangements. This results in degradation of system performance in forms of IQ mismatch, additional noise aliasing and spurious tones. This paper describes a fully automated reference clock duty cycle tuning system for low-power RF circuits. To achieve energy-efficient operation, the method utilizes signal slope and resistor based offset tuning combined with digital feedback system to compensate for measured duty cycle error. The system achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 2 - 7 5} \boldmath{\%}$</tex> tuning range and jitter less than 30 fs over the desired <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40-60$</tex> % range for the targeted <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$24 \text{GS} / \mathrm{s}$</tex> sampling rate.