Evaluating Area-Time-Power Trade-offs in NTT Accelerators for Post-Quantum Cryptography

This study evaluates the trade-offs between area, time, and power in an FPGA-based Number-Theoretic Transform (NTT) hardware accelerator designed for post-quantum cryptography (PQC) applications. Using CRYSTALS-Dilithium parameters as a case study, the proposed architecture integrates Cooley-Tukey and Gentleman-Sande configurations to optimize computational efficiency. A Barrett-based modular reduction enhances power efficiency, while an iterative transformation method minimizes hardware area. Performance analysis on the Artix-7 FPGA in two frequency ranges (10–40MHz and 100–250MHz) demonstrates a balanced trade-off between area-time product and power-performance-area efficiencies. The results highlight the accelerator’s suitability for energy-conscious edge computing and high-throughput cryptographic applications, making it a viable solution for PQC implementations that require optimized resource utilization.