Using UCIe Channel Compliance Simulation for Understanding Substrate/Interposer Design Tradeoffs

Recent advances in IC packaging technology such as 2.5D and 3D integration have enabled the use of smaller dies known as chiplets. Unlike system-on-chip (SoC) designs which are constrained to a single process technology node and large die areas which yield poorly, chiplet-based system-in-package (SiP) designs may incorporate many smaller dies from different processes and technology nodes. The Universal Chiplet Interconnect Express (UCIe) standard provides the most comprehensive protocol for chiplet-to-chiplet communication. It specifies two interconnect channel requirements: VTF Loss and VTF Crosstalk, as well as a receiver eye mask requirement that incorporates both channel and equalization effects. Using the minimal equalization requirements from the UCIe standard during channel compliance SI simulation may underestimate actual receiver eye performance. This is because typical UCIe IP PHYs will likely offer more powerful equalization capabilities. Therefore, to make the right design tradeoffs between cost, SiP floor planning, and electrical performance, it is crucial to identify all forms of equalization available from the vendor’s UCIe PHY IP and incorporate them into the UCIe channel compliance simulation of the receiver eye.