Module Stress Reduction for 2.5D TSV-based Heterogeneous Package

Resilience to mechanical stress is an essential requirement for successful electronics applications. This paper investigates how underfill and metal lid adhesive choice effect module stresses in 2.5D Through Silicon Via (TSV) based heterogeneous packages. Key material properties such as glass transition temperature (Tg), modulus of elasticity and coefficient of thermal expansion (CTE) are critical when package warpage is varied from room to peak (240~260°C) reflow temperatures. Application-specific integrated circuit (ASIC) die (especially in 5 nm wafer node), high-bandwidth memory (HBM) (trending toward HBM3, HBM3E and HBM4 series) as well as larger, thicker substrates are driving a sharp increase in package costs. This increase in material costs makes it difficult to perform engineering evaluations with a sufficiently high sample size. Utilizing mechanical stress simulations is a cost-effective alternative. This paper describes ANSYS module stress simulations run with both flat-top lid and stiffener ring designs of various foot widths and thicknesses. This allows for the assessment of a variety of underfill and metal lid adhesive choices in the different package configurations. Then, when a key configuration is identified, physical test vehicles can be made to confirm simulation results. Using a Chip on Wafer (CoW) assembly test vehicle with 72-mm x 72-mm package size and 39-mm x 35-mm module size, it was determined that the choice of these materials is critical, not only for package warpage management, but also for module resistance against mechanical stress in reliability testing.