Effective fault detection in M3D ICs: a cluster-based BIST for enhanced inter-layer via fault coverage

Monolithic three-dimensional integrated circuits (M3D ICs) have emerged as an innovative solution to overcome the limitations of traditional 2D scaling, offering improved performance, reduced power consumption, and enhanced functionality. Inter-layer vias (ILVs), crucial components of M3D ICs, provide vertical connectivity between layers but are susceptible to manufacturing and operational defects, such as stuck-at faults (SAFs), shorts, and opens, which can compromise system reliability. These challenges necessitate advanced built-in self-test (BIST) methodologies to ensure robust fault detection and localization while minimizing the testing overhead. In this paper, we introduce a novel BIST architecture tailored to efficiently detect ILV defects, particularly in irregularly positioned ILVs, and approximately localize them within clusters, using a walking pattern approach. In the proposed BIST framework, ILVs are grouped according to the probability of fault occurrence, enabling efficient detection of all SAFs and bridging faults (BFs) and most multiple faults within each cluster. This strategy empowers designers to fine-tune fault coverage, localization precision, and test duration to meet specific design requirements. The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters. The method also enhances efficiency in terms of area and hardware utilization, particularly for larger circuit benchmarks. For instance, in the LU32PEENG benchmark, where ILVs are divided into 64 clusters, the power, area, and hardware overheads are minimized to 0.82%, 1.03%, and 1.14%, respectively.