VLPPLAs: Variable Latency Parallel Prefix Ling Adders

ABSTRACT Adders are ubiquitous in computer systems. Parallel prefix adders (PPAs) provide a way to speed up the addition. To further increase the performance, variable latency parallel prefix Ling adders (VLPPLAs) are proposed based on Ling adders in this work, respectively, using Brent–Kung, Beaumont Smith, Knowles, Kogge–Stone, and Sklansky topologies. The parallel prefix processing stage is designed to generate correct sums for most input operands. The Ling carries of these operands propagate for no more than a predetermined maximum carry chain length. The results of the remaining cases are speculated and detected through an overall error detection signal (OEDS) and then may be corrected using exact circuits if it is asserted in the next clock cycle. The OEDS is divided into several block error detection signals (BEDSs), for which the error rates are computed to estimate the computing accuracy of the designed VLPPLAs. Simulation and experimental results indicate that the proposed VLPPLAs achieve reductions in error rates by up to 96.50%, and energy performance with respect to average latency by about 15.68% for 64‐bit designs on average, respectively, compared with previous variable latency parallel prefix adders (VLPPAs).