Development of a GaAs Stacked Cells Based on Common-Gate Model Extraction Procedure

In this paper, the design of a basic self-biased stacked cell using a customized common-gate small-signal model is presented. The model extraction procedure is detailed in the paper and applied to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.1-\mu \mathrm{m}$</tex> GaAs pHEMT with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 40-\mu \mathrm{m}$</tex> periphery, which is used as basic element for the design of the stacked cell. Measurements in common-source configuration together with electromagnetic simulations are used to extract an accurate model of the common gate, that is then validated against measurements in common-gate configuration. Eventually, the design of a 2-transistor stacked cell is reported, together with the simulation results. The designed cell nearly achieves the ideal 3-dB output power improvement with respect to the single device.