Real-Time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems

This paper presents a real-time, energy-efficient embedded system implementing an array of a Cascade of Asymmetric Resonators with Fast-Acting Compression (CARFAC) cochlea models for underwater sound analysis. Built on the AMD Kria KV260 System-on-Module (SoM), the system integrates a Rust-based software framework on the processor for real-time interfacing and synchronisation with multiple hydrophone inputs, and a hardware-accelerated implementation of the CARFAC models on a Field-Programmable Gate Array (FPGA) for real-time sound preprocessing. Compared to prior work, the CARFAC accelerator achieves improved scalability and processing speed while reducing resource usage through optimised time-multiplexing, pipelined design, and elimination of costly division circuits. Experimental results demonstrate 13.5% hardware utilisation for a single CARFAC instance and a whole board power consumption of 3.11 W when processing a 256 kHz input signal in real time.

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Published
2026-04-21
DOI
https://doi.org/10.1109/icassp55912.2026.11463433
Primary Topic
Numerical Methods and Algorithms
Type
article
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article

Real-Time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems

Stuart Anstee, André van Schaik, Gregory Cohen, Ying Xu et al.
Numerical Methods and Algorithms
article

Real-Time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems

Stuart Anstee, André van Schaik, Gregory Cohen, Ying Xu, Bram Bremer, Matthew Bigelow
article en

Abstract

This paper presents a real-time, energy-efficient embedded system implementing an array of a Cascade of Asymmetric Resonators with Fast-Acting Compression (CARFAC) cochlea models for underwater sound analysis. Built on the AMD Kria KV260 System-on-Module (SoM), the system integrates a Rust-based software framework on the processor for real-time interfacing and synchronisation with multiple hydrophone inputs, and a hardware-accelerated implementation of the CARFAC models on a Field-Programmable Gate Array (FPGA) for real-time sound preprocessing. Compared to prior work, the CARFAC accelerator achieves improved scalability and processing speed while reducing resource usage through optimised time-multiplexing, pipelined design, and elimination of costly division circuits. Experimental results demonstrate 13.5% hardware utilisation for a single CARFAC instance and a whole board power consumption of 3.11 W when processing a 256 kHz input signal in real time.

Defence Science and Technology Group (AU), Department of Defence (AU), Western Sydney University (AU)
Openalex Percentile: Top 98%
Numerical Methods and Algorithms
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Real-Time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems — Stuart Anstee, André van Schaik, et al. · (2026) | TGRS Research Map | TGRS