Energy-efficient network-on-chip routers using a power gated Round Robin arbiter ensuring minimal impact on latency

Since the conventional bus-based system does not scale well as the number of cores increases, processor designers are increasingly choosing Network on Chip (NoC) to transfer data using packet-based communication. Every core in a NoC system is linked to a local router, and communication links connect each router to the others. The high power consumption of these routers and links is a serious issue. We have worked on creating an energy-efficient NoC router that uses the power gating technique in order to address this issue. We changed the router's arbitrator block to enable it to turn off unused components when it's not in use. Leakage power is decreased as a result. Our design saves energy without affecting the router's performance, according to our comparison with the conventional Round-Robin arbiter. This work presents the design and FPGA implementation of a power-gated, energy-efficient Round-Robin (RR) arbiter integrated within a NoC router framework. The proposed architecture employs fine-grained power gating with output isolation to selectively deactivate idle modules while maintaining data integrity and fairness in arbitration. A 4×4 synchronous Round-Robin arbiter is modeled in Verilog HDL and synthesized using Intel Quartus II v13.0 targeting FPGA hardware. Power analysis is conducted through the PowerPlay Analyzer under VCD-based switching activity, and functional verification is achieved via ModelSim-Altera simulation. Experimental results demonstrate that the proposed power-gated router achieves a total power reduction of 0.54%, with dynamic power decreasing by 6.25% and I/O power by 2.64%, compared to the baseline non-gated design, while preserving timing closure and throughput. The study confirms that dynamic gating efficiently mitigates switching losses with minimal hardware overhead, though static leakage remains dominant. These findings underscore the potential of adaptive power gating in NoC arbiters to enhance energy efficiency without degrading performance, paving the way for future integration of multi-domain gating, clock control, and dynamic voltage scaling in advanced NoC architectures. • Proposed a power-gated Round Robin arbiter for NoC routers to reduce leakage power. • Achieves energy savings without degrading fairness or latency. • FPGA implementation may confirms 6.25 Percentage reduction in dynamic power. • Demonstrates a low-power, hardware-level solution for NOC.