A Lightweight and Hardware-Efficient NTT FPGA Accelerator for FHE Applications

The Number Theoretic Transform (NTT) and its inverse (INTT) are pivotal operations in Fully Homomorphic Encryption (FHE) schemes to facilitate efficient polynomial multiplication over modular rings. We propose a compact and hardware-efficient NTT/INTT architecture for FHE systems with a novel twiddle factor generator (TFG) for Radix-2 multi-path delay commutator (MDC) designs, saving up to 97.2% of on-chip memory by storing the twiddle factors (TF) for the initial 11 stages (for log<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>(<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i>) = 15 to 17) and only the TF bases for on-the-fly generation in the remaining stages. DSP-efficient multipliers via non-standard tiling are designed to reduce DSP utilization as compared to standard tiling, without sacrificing performance. Benchmarking on comparable Xilinx FPGAs reveals that our design is the most compact, along with a significant efficiency advantage with up to 2.72× reduction in average area-time product (ATP) and up to 2.57× increase in throughput-per-equivalent-LUT (TPE) compared to state-of-the-art NTT designs. In various configurations, the architecture maintains lower BRAM and DSP utilization, and better overall efficiency, making it a scalable and efficient solution for real-world FHE deployments.