Suppression of stacking faults expansion by backside proton implantation into SiC substrates

We demonstrate suppression of single Shockley stacking fault expansion in 4H-SiC PiN diodes by high-energy proton implantation from the substrate side. Proton implantation at 7.9 MeV introduces point defects near the substrate/epilayer interface without degrading the electrical performance of the device. Cathodoluminescence and free carrier absorption measurements confirm defect diffusion and carrier lifetime reduction in the epilayer, correlating with suppression of stacking fault expansion. This backside implantation approach may extend the applicability of the stacking fault knocking-down by high-energy ion implantation method to SiC wafers with a typical thickness of 350 ± 25 μm.

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Publication Details

Journal
Materials Science in Semiconductor Processing
Published
2025-11-14
DOI
https://doi.org/10.1016/j.mssp.2025.110262
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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article

Suppression of stacking faults expansion by backside proton implantation into SiC substrates

Masashi Kato, Shunta Harada, Tong Li, Hitoshi Sakane
Materials Science in Semiconductor Processing
Silicon Carbide Semiconductor Technologies
article

Suppression of stacking faults expansion by backside proton implantation into SiC substrates

Masashi Kato, Shunta Harada, Tong Li, Hitoshi Sakane
article en

Abstract

We demonstrate suppression of single Shockley stacking fault expansion in 4H-SiC PiN diodes by high-energy proton implantation from the substrate side. Proton implantation at 7.9 MeV introduces point defects near the substrate/epilayer interface without degrading the electrical performance of the device. Cathodoluminescence and free carrier absorption measurements confirm defect diffusion and carrier lifetime reduction in the epilayer, correlating with suppression of stacking fault expansion. This backside implantation approach may extend the applicability of the stacking fault knocking-down by high-energy ion implantation method to SiC wafers with a typical thickness of 350 ± 25 μm.

Materials Science in Semiconductor ProcessingVol. 203
Nagoya Institute of Technology (JP), Nagoya University (JP)
Openalex Percentile: Top 66%
Silicon Carbide Semiconductor Technologies
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