ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization

Processors serve as the cornerstone of modern computing systems. Although processor design encompasses multiple VLSI levels, the architectural design plays a critical role in determining performance, power consumption, and area efficiency. To address the growing pressure to shorten chip time-to-market, there is an increasing demand for rapid iteration methods in processor architecture development. To achieve efficient and effortless architecture design optimization, we develop ChatArch, a knowledge-driven graph-of-thought multi-LLM-agent framework for processor architecture optimization. Based on processor architecture expertise, we decompose the processor architecture design space and construct an LLM agent graph-of-thought framework to characterize and iteratively optimize these subspaces. Also, by systematically consolidating domain-specific knowledge and empirical design principles validated by experts, we establish a comprehensive RISC-V processor design knowledge repository. Moreover, a knowledge-driven multi-agent framework is developed to enable efficient microarchitecture optimization. Finally, the optimized microarchitecture modules aggregate to form system-level designs. This methodology achieves automated iterative optimization of microarchitectures targeting PPA objectives while generating corresponding behavioral models. The experiments demonstrate that our method effectively designs behavioral processor models, with LLM-generated architectures achieving a validation success rate of over 97.39%, surpassing the performance of other LLMs, including GPT-4o. ChatArch consistently meets requirements, delivering up to 9.97% times better PPA and 32–68x efficiency gains compared with traditional black-box optimization methods.