Effects of Annealing Temperature Combinations in InOx/AlOx Heterostructure for High-Performance and Stable Solution-Processed Junctionless Transistors

Junctionless (JL) thin-film transistors (TFTs) are promising candidates for low-cost, large-area electronic devices, but improvements in mobility and bias stability are still required. In this study, the effects of independent annealing of the indium oxide (InO_x) channel layer and the aluminum oxide (AlO_x) capping layer (CL) on the performance and reliability of InO_x/AlO_x heterostructure JL TFTs are examined. Devices were fabricated via solution deposition and photopatterning, and the InO_x and AlO_x layers were annealed at 250 °C and 400 °C. Increasing the annealing temperature from 250 °C to 400 °C, the InO_x layer crystallized and densified. The AlO_x layer remained amorphous at both temperatures, but its metal-hydroxyl content decreased with higher annealing. For both layers, JL TFTs annealed at 400 °C exhibited the best electrical performance (threshold voltage = 1.82 ± 0.40 V, subthreshold swing = 0.50 ± 0.07 V dec^-1, saturation mobility = 1.57 ± 0.37 cm² V^-1 s^-1). The threshold voltage shift under positive bias stress was 1.70 V, which demonstrates excellent bias stability. These results show that simultaneous high-temperature annealing of the channel and CL is essential to reduce trap-assisted scattering and stabilize electrostatics in JL TFTs, providing practical process guidelines for bias-stable and high-performance oxide electronics.