Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Off-State Stress With a DC Drain Voltage Bias

The degradation behavior of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small>-state stress (OSS) with a direct current (dc) voltage bias is systematically investigated for the first time. Degradation is governed by the interplay between peak voltage duration, which controls trap emission and hot-carrier (HC) generation, and base voltage duration, which enables trap refilling. The applied dc drain bias further modifies the electric field in the p-n junction, with negative bias enhancing the field and accelerating HC degradation, while positive bias weakens the field and promotes carrier recapture. Supported by experiments and TCAD simulations, a unified emission-recapture model is proposed, offering clear guidance for improving device reliability in circuit applications.