The role of PI thickness and opening dimensions on void suppression in solder bump fabrication

Purpose This study focuses on addressing the voiding issue in bumps during semiconductor packaging. The purpose of this study is to identify optimal parameter combinations to minimize void occurrence and noncompliance rates, thereby enhancing the overall quality and reliability of bump interconnections in high-density integrated circuits. Design/methodology/approach Design of experiments (DOE) is used as the systematic approach. Key parameters, including under-bump metallurgy (UBM) dimensions, polyimide (PI) opening sizes and PI thicknesses, are varied. The experimental data are analyzed using factorial analysis to explore the relationships between factors and responses. Findings Through DOE-based experiments, the influences of different pad materials, wafer materials, UBM dimensions, PI openings and PI thicknesses on void formation are clarified. Optimal combinations of these factors are identified, which can effectively reduce the occurrence of voids in bumps. Originality/value This research systematically investigates the complex interactions of multiple factors on bump voiding using DOE, which is relatively novel in the specific context of bump void studies for this type of semiconductor packaging. The identified optimal parameter combinations provide practical guidelines for the semiconductor packaging industry, enabling improvements in device reliability and reducing potential failure risks.