A memristor-based energy-efficient compressed sensing accelerator with hardware–software co-optimization for edge computing

Compressed sensing (CS), a revolutionary signal processing technique enabling sub-Nyquist sampling, has become integral to reduce hardware cost and energy consumption in diverse applications. However, with the exponential growth of data, traditional Si complementary metal-oxide semiconductor (CMOS)-based hardware implementations face significant challenges, including the von Neumann bottleneck in energy efficiency and computing latency. In this work, we propose a memristor-based CS accelerator (memCS) that leverages computing-in-memory (CIM) to eliminate the data movement overhead. Using a fully integrated 128 Kb memristor chip, we systematically analyze the impact of non-ideal device characteristics, and further propose a hardware-software co-optimization framework that integrates the measurement matrix modification (MMM) and sparsity enhancement (SE) strategies, leading to significantly enhanced noise robustness and reconstruction accuracy. Our memCS eventually achieves a near-software peak signal-to-noise ratio (PSNR) of 31.11 dB and a high accuracy of 94.2% in the image classification task on the ImageNet dataset. Benchmarking results further demonstrate that the memCS greatly outperforms state-of-the-art CMOS hardware by achieving 11.22 times speedup and 30.46 times energy savings, thereby providing a scalable solution for energy-efficient edge computing applications.