Principle and Verification of D-Latch Circuit Using Photoelectric-Motivated Memristor for Shift Register Design

Integrating memristors into D-latch design can potentially cut the power consumption and cost of sequential logic circuits. However, it’s challenging to further minimize the element count in latches with memristor-based logic gate designs. This paper presents a novel approach for constructing D-latches and D flip-flops (DFF) using photoelectric-motivated memristors. These memristors convert optical to electrical signals. For further validation, the newly designed DFFs were cascaded into a shift register for application testing. Simulation tests of the circuits were performed on Multisim and the physical realizability of signal transmission in the design was verified using a Field Programmable Gate Array (FPGA). The test was performed at 3.3[Formula: see text]V and 27 ∘ C. The paper also discusses and analyzes the benefits of using photoelectric-motivated memristors to construct the sequential logic circuits. This work completed the construction of a D-latch using only 4 photoelectric-motivated memristors and 3 resistors. Moreover, the photoelectric-motivated memristor used in this work is silicon-based and compatible with the current Complementary Metal-Oxide-Semiconductor (CMOS) process, enabling large-scale integration.