Enforcing RISC-V TEE Security Against Cache Timing Attacks

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SPIRE - Sciences Po Institutional REpository
Published
2025-06-15
Primary Topic
Security and Verification in Computing
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article
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article

Enforcing RISC-V TEE Security Against Cache Timing Attacks

Vianney Lapôtre, Pascal Cotret, Loïc Lagadec, Oussama Elmnaouri
SPIRE - Sciences Po Institutional REpository
Security and Verification in Computing
article

Enforcing RISC-V TEE Security Against Cache Timing Attacks

Vianney Lapôtre, Pascal Cotret, Loïc Lagadec, Oussama Elmnaouri
article en

Abstract

No abstract available for this paper.
SPIRE - Sciences Po Institutional REpository
Université de Bretagne Occidentale (FR), École Nationale Supérieure de Techniques Avancées (FR), Université de Bretagne Sud (FR), École Nationale Supérieure de Techniques Avancées Paris (FR)
Openalex Percentile: Top 82%
Security and Verification in Computing
OpenAlex
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Enforcing RISC-V TEE Security Against Cache Timing Attacks — Vianney Lapôtre, Pascal Cotret, et al. · SPIRE - Sciences Po Institutional REpository (2025) | TGRS Research Map | TGRS