Simulation of a cyclic redundant encoder for data transmission by Ethernet II frames in the Xilinx Vivado environment

The article reveals the relevance of the family of wired computer network technologies Ethernet used to transmit data streams in local, metropolitan and global networks. The historical retrospective and evolution of the development of Ethernet technologies are considered. The role of cyclic redundancy coding (CRC), which is widely used in data transmission protocols, including Ethernet, for detecting errors in data by adding a special code to each block is shown. The choice of the Ethernet II frame type, as the most common for data transmission in local networks, is substantiated. The data structure of the Ethernet II frame, containing a preamble, network addresses of the recipient and sender, information about the Internet protocol version, a variable-length data field from 46 to 1500 bytes and CRC, is investigated. The principle of calculating a 4-byte CRC for the data structure of the Ethernet II frame using the 32-bit polynomial 0x04C11DB7 is described. A functional diagram and an algorithm for modeling a CRC encoder have been developed. The source code of the CRC encoder has been created in the Verilog programming language. It uses the bit reflection function for calculations using the inverse polynomial 0xEDB88320. A special program for testing the encoder has been developed. It forms a stream of Ethernet II frames consisting of the recipient and sender addresses, an Internet protocol type field, a random-length payload, and an interframe interval of 12 to 24 bytes of zeros. The encoder operation has been simulated in the Xilinx Vivado FPGA development environment on a stream of Ethernet II frames that lack an 8-byte preamble, since it is not taken into account when calculating the 32-bit CRC for the frame. The resulting timing diagrams have been analyzed. The calculation results have been checked in the online CRC calculator.