Low-Power Analog and RF Performance Analysis of a Nanowire Junctionless TFET with Dual-Metal-Insulator-Semiconductor (DMIS) Structure for Communication Systems

This paper examines how a Gate All Around (GAA) Junctionless Tunnelling Field-Effect Transistor (JLTFET) performs under two different configurations: Metal-Dielectric-Semiconductor (MDS) GAA-JLTFET and Metal-Dielectric-Metal-Insulator-Semiconductor (DMIS) GAA-JLTFET. Compared to the former, the latter suggested device successfully mitigates the subthreshold swing (SS) of the device. It achieves a reduced SS of about 15 mV/decade, a substantial on state current of around 1.69 mA/µm and a noteworthy lower off state current of about 10–18 A/µm, possibly attributed to the elevated-k dipole at the oxide-semiconductor interface impeding source tunneling current in the off state. The influence of high-k dielectric materials on the performance of the proposed device is simulated using ATLAS tool. The device parameters are fine-tuned to diminish the off current and to improve the SS, ensuring that the suggested device is well applicable for low-power, analog, and radio frequency (RF) applications.