Fine-Pitch Die-to-Wafer Bonding Technologies for Chiplet Integration

Chiplet technology allows the combination of Si blocks with own intellectual property (IP) and standardized surfaces in order to reach higher value heterogeneous miniaturized systems. Chiplets will play a crucial role in a future packaging, because they allow split manufacturing and propose a cost-effective solution. However, this technology is still new and numerous questions in terms of architecture, design and packaging need to be investigated. Chiplets arriving from different fabs can have different interconnect finishes, which means that a coordinated bonding profile should be established. The focus of the current study is the fabrication and technology development of three different interconnect types, which can be applicable for chiplet integration. We report on development of hybrid, microbump and nanowire die-to-wafer bonding technologies with a pitch size of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10 \mu \mathrm{m}$</tex> on a test chiplet design. The test chiplets are designed to be bonded on a Si interposer with a Cu/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> hybrid bond finish for possible applications in high-performance computing. The results show the processing details and characterization of the assemblies performed for each chiplet type. The chiplets with hybrid bonding and microbump surfaces were successfully assembled together onto one interposer, demonstrating a principal possibility of the interconnect technology combination.