Performance Study of Sub-5 nm FinFET and GAA Structures at Low Temperature

This work investigates the cryogenic performance of 5 nm FinFET and Gate-All-Around (GAA) transistors, focusing on their electrical, thermal, and noise properties. Both devices exhibit better transconductance (gm), threshold voltage (Vth), drain current (IDS), subthreshold swing (SS), leakage current, on/off ratio, and noise figure (F) at low temperatures. FinFETs show maximum transconductance of 79.3 µS, an SS of about 20 mV/dec, and an on/off current ratio of about 1035 at low temperature. They can drive currents of up to 341 µA at 20 K. GAA transistors, on the other hand, have better electrostatic control, with a higher Vth (0.73 V vs. 0.65 V for FinFET), a sharper SS of around 10 mV/dec, and a better on/off current ratio of about 1049. Thermal study indicates that FinFETs exhibit higher self-heating (~91 K) than GAA (~80.5 K), with heat concentrated near the drain end of the channel in FinFETs and near the source end of the channel in GAA transistors. Noise study shows that both thermal and generation–recombination noises are lower at cryogenic temperatures. Multi-gate wrapping can further reduce these noises. Overall, at cryogenic temperatures, the 5 nm FinFET architecture is more suitable for high-current electronics, whereas GAA transistors are more favourable for low-noise and low-power electronics, demonstrating their potential applications in quantum computers and other cryogenic technologies.

Authors

Institutions

Publication Details

Journal
Semiconductors
Published
2025-11-12
DOI
https://doi.org/10.1134/s1063782625601979
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Performance Study of Sub-5 nm FinFET and GAA Structures at Low Temperature

B. C. Joshi, Ajeet Kumar
Semiconductors
Advancements in Semiconductor Devices and Circuit Design
article

Performance Study of Sub-5 nm FinFET and GAA Structures at Low Temperature

B. C. Joshi, Ajeet Kumar
article en

Abstract

This work investigates the cryogenic performance of 5 nm FinFET and Gate-All-Around (GAA) transistors, focusing on their electrical, thermal, and noise properties. Both devices exhibit better transconductance (gm), threshold voltage (Vth), drain current (IDS), subthreshold swing (SS), leakage current, on/off ratio, and noise figure (F) at low temperatures. FinFETs show maximum transconductance of 79.3 µS, an SS of about 20 mV/dec, and an on/off current ratio of about 1035 at low temperature. They can drive currents of up to 341 µA at 20 K. GAA transistors, on the other hand, have better electrostatic control, with a higher Vth (0.73 V vs. 0.65 V for FinFET), a sharper SS of around 10 mV/dec, and a better on/off current ratio of about 1049. Thermal study indicates that FinFETs exhibit higher self-heating (~91 K) than GAA (~80.5 K), with heat concentrated near the drain end of the channel in FinFETs and near the source end of the channel in GAA transistors. Noise study shows that both thermal and generation–recombination noises are lower at cryogenic temperatures. Multi-gate wrapping can further reduce these noises. Overall, at cryogenic temperatures, the 5 nm FinFET architecture is more suitable for high-current electronics, whereas GAA transistors are more favourable for low-noise and low-power electronics, demonstrating their potential applications in quantum computers and other cryogenic technologies.

SemiconductorsVol. 59(12)
Jaypee Institute of Information Technology (IN)
Openalex Percentile: Top 67%
Advancements in Semiconductor Devices and Circuit Design
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Performance Study of Sub-5 nm FinFET and GAA Structures at Low Temperature — B. C. Joshi, Ajeet Kumar · Semiconductors (2025) | TGRS Research Map | TGRS