Design and Test of a 3-Terminal Work-Function Engineered Universal Gate and Modelling of Its Static Performance Metrics

This work presents a 90 nm work-function engineered universal gate design using a non-aligned double-gate technology (wfe-NADGFET), this work aims to reduce the transistor count and improve the power-delay performance at lower supply voltage i.e., 0.5 V. Unlike universal gate implemented using a conventional complementary metal oxide semiconductor (CMOS) technology or a double gate field effect transistor (DGFET), the structure has four gate-input terminals, however the design proposed in this work will realize the same function using three gate-input terminals. The proposed wfe-NADGFET structure uses silicon dioxide as gate oxide and the metal work function engineering method to realize NAND and NOR logic functions. Also, this work uses conventional sub-threshold equation to model the static performance metrics and compares with simulation measurement results. The test input is given a 0.5 V peak square waveform oscillating at 1.0 GHz frequency, the wfe-NADGFET NAND, and NOR, gate yields a propagation delay of 8.36 ps, and 13.33 ps, respectively. Compared with the past universal gates the presented structure operates with a 28.6% less in supply voltage. The paper concludes that proposed structure can give less propagation delay by operating at low supply voltage and high frequency.