Universal Digital Calibration of Mismatched DACs: Enabling Sub-0.02 mm2 Area with Redundancy and Segmented Correction

This paper presents a novel methodology for the design and calibration of ultra-compact digital-to-analog converters (DACs), integrating architectural redundancy and a digital calibration algorithm. The proposed calibration approach generates pre-distortion codes that correct both positive and negative nonlinearity errors, even in designs with severe mismatch or relaxed layout constraints. This enables the use of aggressively scaled devices while maintaining high linearity and spectral fidelity. The algorithm is architecture-agnostic and compatible with resistor-string, current-steering, and hybrid DAC structures. It operates with minimal memory, low latency, and supports both foreground and background calibration modes. The method is validated through simulation and silicon measurement of three 14-bit DAC architectures fabricated in TSMC 180 nm CMOS. Post-calibration results demonstrate linearity within ±0.5–1.2 LSB, ENOB up to 13.8 bits, and significant improvements in SNR, SFDR, and THD. The compact layouts—occupying as little as 0.0169 mm2—highlight the scalability of the proposed method for applications such as analog AI accelerators and high-density mixed-signal SoCs.