A Passage-Based Fault-Tolerant Routing Method for 3D Mesh NoCs Without Creating Faulty Regions

This paper proposes a novel fault-tolerant routing method without creating faulty regions for 3D mesh Network-on-Chips (NoCs). Most conventional methods create faulty regions containing faulty nodes and route packets around them to reach the destinations. However, the creation of faulty regions results in low communication performance and low node utilization. To overcome the two problems, the proposed method does not create faulty regions based on the idea of predefining paths in the absence of shortest paths while allowing the passage of faulty nodes. Simulation results show that, compared with conventional methods, the proposed method reduces average latency by about 44.5% and improves node utilization rate by about 41.2% for 3D mesh NoCs of 5×5×5 nodes.

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Publication Details

Journal
Chips
Published
2025-11-11
DOI
https://doi.org/10.3390/chips4040049
Primary Topic
Interconnection Networks and Systems
Type
article
Field-Weighted Citation Impact
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article

A Passage-Based Fault-Tolerant Routing Method for 3D Mesh NoCs Without Creating Faulty Regions

Yota Kurokawa, Masaru Fukushi
Chips
Interconnection Networks and Systems
article

A Passage-Based Fault-Tolerant Routing Method for 3D Mesh NoCs Without Creating Faulty Regions

Yota Kurokawa, Masaru Fukushi
article en

Abstract

This paper proposes a novel fault-tolerant routing method without creating faulty regions for 3D mesh Network-on-Chips (NoCs). Most conventional methods create faulty regions containing faulty nodes and route packets around them to reach the destinations. However, the creation of faulty regions results in low communication performance and low node utilization. To overcome the two problems, the proposed method does not create faulty regions based on the idea of predefining paths in the absence of shortest paths while allowing the passage of faulty nodes. Simulation results show that, compared with conventional methods, the proposed method reduces average latency by about 44.5% and improves node utilization rate by about 41.2% for 3D mesh NoCs of 5×5×5 nodes.

ChipsVol. 4(4)
Yamaguchi University (JP)
Openalex Percentile: Top 61%
Interconnection Networks and Systems
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