A Subsampling Phase-Locked Loop with a Dual Charge Pump Based on Capacitor Multipliers for CMOS Image Sensor

Traditional zero-compensation techniques employed to improve sub-sampling phase-locked loop (SSPLL) stability often exacerbate spur degradation or incur excessive area overhead, rendering them unsuitable for high-resolution image sensor applications. This paper proposes a novel SSPLL based on capacitor multiplication technology. This capacitor multiplication technology employs dual charge pumps (CP1 and CP2) in a coordinated operational scheme where their charge/discharge states are inversely synchronized. The effective capacitance of the loop filter is thereby amplified without expanding the physical layout area dedicated to capacitive components. Meanwhile, the continued use of zero-compensation technology ensures the stability of the SSPLL. The proposed SSPLL is designed and verified in a 55 nm CMOS process. At a 1.2 GHz output frequency, simulation results show a spot phase noise of -131.5 dBc/Hz at 1 MHz offset, accompanied by an integrated RMS jitter of 549 fs across the 10 kHz to 40 MHz spectrum, spurs suppressed to -51.3 dB, while maintaining a power efficiency of 3.81 mW and a compact layout area of 0.064 mm². All the above results show that by introducing the novel dual-CP charge multiplication technology, the SSPLL can achieve low jitter and low power consumption performance while reducing the layout area, providing a new technical approach for its application in high-resolution image sensors.