Bayesian Neural Network Realization by Exploiting Random Noise and Mitigating the Impact of Conductance Drift of PCM

Abstract Bayesian neural networks (BNNs) provide inference with uncertainty prediction, which is critical for safety‐sensitive applications such as autonomous driving and medical diagnosis. However, conventional implementations relying on Gaussian random number generators incur significant area and power overheads. In this work, the inherent random noise of phase change memory (PCM) devices are exploited to realize a compact, energy‐efficient BNN hardware architecture. The fabricated 4‐Mb indium‐doped Ge 2 Sb 2 Te 5 (In ‐ GST) PCM chip achieves a resistance ratio of over 190 times and can be programmed to 32 different conductance states. To mitigate the impact of conductance drift on inference accuracy, two compensation methods are proposed, with the measured minus fit method demonstrating superior reduction of epistemic uncertainty. The proposed PCM‐based BNN architecture achieves a MNIST recognition accuracy of 98.08% on LeNet‐5 and demonstrates an energy efficiency of 33.3 TOPS/W. This work establishes a unified memory‐computation‐randomness framework for probabilistic neural network hardware, enabling low‐power and reliable inference with uncertainty quantification.