Lossless Non‐Volatile Post‐Fabrication Trimming of Silicon Photonics Through On‐Chip High‐Temperature Annealing of Undercut Waveguides

ABSTRACT Limited by process precision for silicon photonic integrated circuits (Si‐PICs), manufacturing deviations in waveguide width, etch depth, and layer thickness are inevitable. These variations cause initial phase shifts and compromise the performance of phase‐sensitive devices such as Mach‐Zehnder Interferometers (MZI) and microring resonators. To address this issue, we present a lossless, nonvolatile, and CMOS‐compatible post‐fabrication trimming method based on on‐chip high‐temperature annealing, assisted by highly thermally isolated undercut waveguides. The significant thermal stress during annealing exceeds the yield strength of silicon and induces microscopic modifications including irreversible lattice expansion verified by transmission electron microscopy, which ultimately reduces the mode effective refractive index. This novel approach requires no additional equipment beyond the standard CMOS fabrication and eliminates static power consumption after short‐duration electrical stimulus. Trimming experiments on C‐ and O‐band MZIs demonstrated a phase compensation over 4π, a tuning resolution over 6 bits, and stable operation beyond 8500 hours. Additionally, 15 randomly MZIs are precisely trimmed to BAR, CROSS, or orthogonal states, confirming the method's universality. This practical technique enables reliable, scalable post‐fabrication trimming for low‐cost, energy‐efficient Si‐PIC applications such as optical modulating, switching, and computing.