Gate Dielectric Engineering Using Stacked Gate Dielectric in U‐Shaped Gate Tunnel FET

In this paper, an innovative approach for the performance enhancement of tunnel field‐effect transistors (TFETs) is presented with the introduction of the stacked gate oxide U‐shaped tunnel FET (SUTFET). This novel design incorporates a unique combination of titanium dioxide (TiO 2 ) and silicon dioxide (SiO 2) layers as stacked gate dielectrics, significantly enhancing device performance. The stacked SUTFET achieves a notable reduction in the OFF‐current while delivering a substantial improvement in the ON‐current and better subthreshold swing (SS). Our research explores varying the thickness of TiO 2 and SiO 2 layers effect on critical electrical parameters, including threshold voltage, ON‐current, and leakage current. This study reveals that the use of TiO 2 , with its superior dielectric constant compared to the conventional HfO 2 , leads to exceptional current capabilities and superior control over the off current. Through detailed simulations, we demonstrate that the adjustment of dielectric thickness can further optimize SS and minimize the leakage. The findings highlight the potential of the stacked gate oxide SUTFET as a major breakthrough in the field of tunnel FETs, paving the way for advancements in high‐performance and low‐power electronic devices. This novel approach not only addresses key performance limitations of conventional TFET structures but also sets a new benchmark for future research and development in the semiconductor technology.