A CMOS Voltage Reference with PTAT Current Using DIBL Compensation for Low Line Sensitivity

This paper presents a low-power CMOS voltage reference with low supply sensitivity, designed and verified in a 180 nm standard CMOS technology. A DIBL-based line-sensitivity (LS) compensation path is incorporated into the conventional PTAT generation circuit to simultaneously provide a reference voltage and a bias current with improved LS. The proposed circuit achieves LS values of 0.01%/V for the voltage reference and 0.07%/V for the bias current reference over a supply voltage range of 1.4 V to 2 V. It generates a reference voltage of 538 mV and a PTAT current of 38 nA, consuming 68 nW. The simulated temperature coefficient is 58 ppm/℃ from -40 °C to 130 °C, and the power supply rejection ratio is -59 dB at 100 Hz.