Design of a Novel Low-Power Dual Switching Circuit for Hybrid CMOS/SOT-MTJ Logic

The search for next-generation technologies has become essential due to the bottlenecks of complementary metal-oxide-semiconductor (CMOS) technology. As technology evolves, downscaling of CMOS transistors faces challenges like high power consumption, heat dissipation and quantum effects. These issues hinder further performance and efficiency improvements. To address these limitations, researchers are focusing on alternatives such as spintronics, memristors and quantum computing. Magnetic tunnel junctions (MTJs) stand out for their low power consumption, fast interconnects, CMOS compatibility and inherent nonvolatility. These features make them ideal for ultra-dense memory circuits. A hybrid CMOS/MTJ design presents significant opportunities for low-power data-intensive applications. Spin-orbit torque (SOT) offers higher writing endurance than spin-transfer torque (STT) because of its distinct read and write paths. Effective spin manipulation through SOT in MTJs is crucial for enabling low-power logic and memory functions. This paper proposes a novel energy-efficient dual read/write switching circuit with resistor-based biasing, tailored for nonvolatile combinational circuits. The proposed switching circuit is used to design a nonvolatile AND/NAND logic circuit as a case-study implementation. The simulation results are based on a 45-nm CMOS process design kit and a Verilog-A SOT MTJ model integrated into the Cadence Virtuoso platform. The proposed design demonstrates a power-delay-product (PDP) efficiency of 83.4% and an area efficiency of 45.45% based on device count. Monte Carlo (MC) simulations were conducted to account for process variations in CMOS transistors, ensuring the operational stability of the proposed writing circuit.